In modern electronic systems, such as computers, telephone exchanges and others, data has to be transmitted, for example, between integrated circuits (ICs) located on a printed circuit board (PCB) or between different boards. To achieve a high transmission speed while keeping power dissipation low, differential data lines are getting more and more importance.
FIG. 1 illustrates a simplified block diagram of data transmission system 10 according to the "Draft Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)", Draft 1.3 IEEE P1596.3-1995. System 10 comprises lines 1 and 2, driver 3 (or "transmitter module"), symmetrically arranged load resistors 4 and 5 (each having equal values, e.g., R.sub.1 =R.sub.2= 50 .OMEGA.), and voltage sources 6 and 7, coupled as illustrated. Usually, lines 1 and 2 each have a length of several meters (maximum about 10 meters).
Line voltages V.sub.1 and V.sub.2 and rated voltage V.sub.RATED are defined to ground 8 (e.g., potential GND .apprxeq.zero)). A voltage swing .DELTA.V is defined as being positive. The terminating voltage V.sub.CENTER is defined between node 9 (coupling resistors 4 and 5) and ground 8 (potential GND).
Driver 3 differentially transmits binary signals having first and second logical values (differential mode (DM) transmission). Driver 3 either
(a) simultaneously pulls lines 1 and 2 to EQU V.sub.1 =(V.sub.RATED +.DELTA.V), and EQU V.sub.2 =(V.sub.RATED -.DELTA.V), (2) PA1 (b) simultaneously pulls lines 1 and 2 to EQU V.sub.1 =(V.sub.RATED -.DELTA.V), and EQU V.sub.2 =(V.sub.RATED +.DELTA.V). (4)
or
Convenient values for rated voltages are V.sub.RATED)= 1200 mV (milli volts). The voltage swing is conveniently .DELTA.V&lt;250 mV (.DELTA.V.sub.MAX= 250 mV). In other words, in case (a), the positive voltage difference EQU (V.sub.1- V.sub.2)=2*.DELTA.V (6)
represents a first logical value; and in case (b), the negative voltage difference EQU (V.sub.1- V.sub.2)=-2*.DELTA.V (8)
represents a second, opposite logical value.
Changes between logical values can conveniently be transmitted at data rates up to 250 megabit per second (MBs). Higher rates, e.g., up to 850 MBs (or even higher) are also possible.
Neglecting the current from node 9 to ground 8, currents I.sub.1=.sub.2 =I through lines 1 and 2 are limited to ##EQU1##
The .vertline. .vertline. symbols stand for absolute values.
However, the differential signal transmission is subject to common mode (CM) fluctuations. For example, voltage V.sub.CENTER at node 9 can have the following time function: EQU V.sub.CENTER (t)=V.sub.DC +V.sub.AC * sin (2*.pi.*f*t) (12)
Usual values are V.sub.DC =V.sub.RATED and V.sub.AC =V.sub.RATED (a.c. amplitude). The fluctuation frequency f can have magnitudes from substantially zero to about 1000 MHz (i.e., four times the data rate). The common mode fluctuations should not influence the differential mode signal transmission.
Driver 3 should drive both lines symmetrically over the whole range of V.sub.CENTER. The standard requires a specific internal resistance for output of driver 3 so that no reflections arise at the output even with returning waves potentially occurring due to asymmetries or disturbances. In other words, there is a need to match the impedances of driver output, transmission lines and load. A transmission gate providing proper impedance is explained in U.S. Pat. No. 5,559,448 to Koenig.
In other words, there is a requirement to provide such a driver which keeps its output resistance for both lines constant and linear over the whole magnitude range of V.sub.CENTER (cf. equation (12)).